1. Field of the Invention
This disclosure relates to a semiconductor device and, more particularly, to a dynamic random access memory (DRAM) and a method of manufacturing the same.
2. Description of the Related Art
As technologies for manufacturing semiconductor devices have been developed and applications for memory devices have been expanded, memory devices having large capacities have been required. In particular, an integration density of a DRAM device wherein a memory cell is composed of one capacitor and one transistor has been remarkably improved.
Accordingly, as an integration density of a semiconductor device increases, a size of the contact hole connecting one element to another element or one layer to another layer decreases but a thickness of interlayer dielectric layer increases. Thus, in a photolithographic process, an aspect ratio of the contact hole, i.e., a ratio of a length of a hole relative to its diameter, is increased while an alignment margin of the contact hole decreases. As a result, formation of a small contact hole becomes very difficult using conventional methods.
As for a DRAM device, a method for forming a landing pad is widely used to reduce the aspect ratio of the contact hole and a self-aligned contact (SAC) structure is employed to a pattern having a feature size of about 0.1 um or less to correct a short-circuit problem caused by a reduction of the alignment margin.
FIGS. 1A, 2A, 1B, and 2B are cross-sectional diagrams illustrating a method of manufacturing a DRAM device having an SAC structure according to a conventional method. FIGS. 1A and 2A are cross-sectional diagrams along a bit line direction of the DRAM device and FIGS. 1B and 2B are cross-sectional diagrams along a word line direction of the DRAM device.
Referring to FIGS. 1A and 1B, isolation regions 12 are formed on a semiconductor substrate 10 to define active regions using a common isolation process such as a shallow trench isolation (STI) process.
Metal oxide semiconductor (MOS) transistors having gate electrodes 14 serving as the word lines and source/drain regions (not shown) are formed on the substrate 10. Gate capping layer patterns 16 composed of nitride are formed on the gate electrode 14 and gate spacers 18 composed of nitride are formed on sidewalls of the gate electrode 14.
A first interlayer dielectric layer 20 composed of oxide is formed on an entire surface of the substrate 10 including the MOS transistors. The first interlayer dielectric layer 20 is planarized by a chemical mechanical polishing (CMP) process or an etch-back process. Using an etching gas having an etching selectivity relative to nitride, the first interlayer dielectric layer 20 is etched to from contact holes that are self-aligned relative to the gate electrodes 14. The contact holes expose the source/drain regions of the MOS transistors.
A doped polysilicon layer is formed on the first interlayer dielectric layer 20 and the contact holes. The doped polysilicon layer is separated into node units by a CMP process or an etch-back process so that SAC pads 22a and 22b are formed in the contact holes. The SAC pads 22a and 22b are connected to the source/drain regions, respectively.
A second interlayer dielectric layer 24 composed of oxide is formed on the first interlayer dielectric layer 20 and on the SAC pads 22a and 22b. The second interlayer dielectric layer has a thickness of about 1,000˜3,000 Å. The second interlayer dielectric layer 24 is planarized by a CMP process or an etch-back process. With a common photolithographic process, the second interlayer dielectric layer 24 is partially etched to form bit line contact holes (not shown) exposing some SAC pads 22b positioned on the drain regions.
A barrier metal layer (not shown) composed of titanium/titanium nitride (Ti/TiN) and a first conductive layer 26 for bit lines 30 are sequentially formed on the second interlayer dielectric layer 24 and the bit line contact holes. The first conductive layer 26 is formed to have a thickness of about 400˜800 Å. A nitride film is formed on the first conductive layer 26 to have a thickness of about 1,000˜3,000 Å so that a bit line mask layer 28 is formed. The bit line mask layer 28 and the first conductive layer 26 are etched by a photolithographic process, thereby forming the bit lines 30 including the first conductive layer 26 and the bit line mask layer 28. At this time, to enlarge an insulation space (i.e., shoulder) between the bit line 30 and a storage node contact hole during a subsequent process of forming the storage node contact holes, the bit line mask layer 28 should be thickly formed to have a thickness of about 200 Å or more.
A material having an etching selectivity relative to a third interlayer dielectric layer successively formed in a subsequent process, e.g., nitride, is deposited on the bit lines 30 and the second interlayer dielectric layer 24. The material is anisotropically etched to form bit line spacers 32 on sidewalls of the bit lines 30. Since the etching process of forming the bit line spacers 32 composed of nitride is performed directly after formation of the bit lines 30, a surface of the bit line mask layer 28 composed of identical material, i.e., nitride, is partially damaged.
The third interlayer dielectric layer 34, composed of boro-phospho-silicate glass (BPSG), undoped silicate glass (USG), high density plasma (HDP) oxide, or chemical vapor deposited (CVD) oxide, is formed on an entire surface of the resultant structure. The third interlayer dielectric layer 34 is planarized by a CMP process or an etch-back process.
Referring to FIGS. 2A and 2B, with a photo process, photoresist patterns (not shown) for defining storage node contact hole regions are formed on the third dielectric layer 34. Using an etching gas having a high etching selectivity relative to the bit line spacers 32 composed of nitride, the third interlayer dielectric layer 34 and the second interlayer dielectric layer 24 are dry etched to form the storage node contact holes 36 exposing the SAC pads 22a on the source regions. In this case, the interlayer dielectric layers 34 and 24 should be over etched so as to prevent the storage node contact holes 36 from being not opened. Accordingly, recesses of the bit line mask layer 28 are generated to deteriorate shoulder portions between the bit lines 30 and the storage node contact holes 36.
After removing the photoresist patterns, a second conductive layer composed of doped polysilicon is formed to fill up the storage node contact holes 36, the second conductive layer is separated into node units by a CMP process or an etch-back process, thereby forming storage node contact pads 38 separated into node units in the storage node contact holes 36.
According to the conventional method, a thickness of the bit line mask layer 28 composed of nitride should be increased so as to ensure an SAC process margin so that a height of the bit line 30 may increase. On the contrary, as a design rule of the pattern decreases to about 0.1 μm or less, a space between adjacent bit lines 30 becomes smaller, thereby increasing an aspect ratio of the bit line 30. Additionally, when the third interlayer dielectric layer 34 is formed in a state in which the bit line spacers 32 are formed on the sidewalls of the bit lines 30, the space between the bit lines 30 becomes so narrow that the aspect ratio of the bit lines 30 greatly increases. As a result, a gap between the bit lines 30 may be not fully filled with the third interlayer dielectric layer 34 and voids may be generated in the third interlayer dielectric layer 34.
When the voids are formed in third interlayer dielectric layer 34 as described above, the voids may expand during a subsequent cleaning process. Hence, when the second conductive layer for the storage node contact pad is formed, the second conductive layer may penetrate into the enlarged voids so that the storage node contact pad 38 may be connected to an adjacent storage node contact pad 38. As a result, a bridge may be generated between the storage node contact pads 38.
When the thickness of the bit line mask layer 28 increases to ensure the SAC process margin, a thickness of the photoresist film for forming the bit lines should be augmented, thereby causing the lifting of the bit line 30 due to the photoresist film falling down.
Furthermore, since the bit line mask layer 28 may be damaged during the etching processes of forming the bit line spacers 32 and forming the storage node contact holes 36, the bit lines 30 are electrically short-circuited relative to the storage node contact pads 38, thereby generating single bit failures.
The bit lines correspond to wirings for detecting the existence of charges stored on memory cells of the DRAM device. The bit lines are generally connected to sense amplifiers positioned in a peripheral circuit region of the DRAM device. The variation of the bit line voltage is detected by detecting the charges stored on the memory cells, and the voltage variation increases accordingly as a storage capacitance of the memory cell increases or a bit line loading capacitance decreases. Accordingly, since the decrease of the bit line loading capacitance improves a sensitivity of the sense amplifier, it is preferable to decrease the bit line loading capacitance as much as possible for the improvement of reliability and response speed.
In the conventional method, a parasitic capacitance, i.e., the bit line loading capacitance between the bit line 30 and the storage node contact pad 38 or between the bit line 30 and an adjacent bit line 30, increases. This occurs because the bit-line spacers 32 composed of nitride having a high dielectric constant are formed on the sidewalls of the bit lines 30 to ensure the shoulder margin of the bit lines in accordance with the SAC process. Because a capacitance of a capacitor increases in accordance with a decrease of a thickness thereof, the thickness of the bit line spacer 32 becomes smaller as the design rule of the pattern decreases, thereby greatly increasing the bit line loading capacitance. Thus, the number of the bit lines constituting a cell array of the DRAM device should be reduced considering the bit line loading capacitance, which results in a reduction of cells per unit bit line and deteriorates chip efficiency.
In U.S. Pat. No. 6,458,692 and Japanese Laid Open Patent Publication No. 2001-217405, there are disclosed methods of forming contacts wherein spacers composed of silicon oxide having a low dielectric constant are formed on sidewalls of bit lines so as to reduce a bit line loading capacitance. However, the reduction of the thickness of a bit line mask layer may be limited to decrease the gap-fill margin of an interlayer dielectric layer. Additionally, there is scarcely any shoulder margin of the bit line, which results in a generation of an electrical short-circuit between the bit line and a storage node contact pad.
Embodiments of the invention address these and other limitations of the prior art.